This application claims priority to GB Application No. 0624875.1 filed Dec. 13, 2006, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data transfers between initiators and recipients or masters and slaves.
2. Description of the Prior Art
Initiator and recipient devices, such as masters and slaves often operate at different frequencies, the master generally operating at a higher frequency than the slave. This can lead to problems when communicating data between the two devices. This problem is addressed by utilising a clock enable signal which basically acts to enable the input and output of the devices to ensure that data is only transmitted at a frequency governed by the clock enable signal. Thus, the frequency of this signal can be set to account for the lower frequency of the communicating devices and thereby ensure that the data communication is performed at a frequency that allows the lower frequency device to receive data at a rate it can cope with. In the AXI bus produced by ARM® only integer ratios of clock frequencies are allowed between the master and slave.
This severely limits possible frequencies that the slave can operate at. It can operate at the same frequency as the master or at this frequency divided by a factor of 2. This limitation in possible frequencies can be a limiting factor to some performance requirements.
It would be advantageous if more flexibility in clock ratios between the master and slaves could be allowed.